The present invention relates to integrated circuit technology and to resistive random-access memory (ReRAM) technology. More particularly, the present invention relates to integrated circuit layouts for addressable arrays of ReRAM memory cells employing small geometry transistor devices such as FinFET transistor devices. ReRAM memory cells have been employed as configuration memory for user-programmable integrated circuits by driving a switch transistor that configures a programmable circuit. ReRAM memory cells have also been used as random-access memory (RAM) in integrated circuits. The present invention relates to ReRAM memory cells used in integrated circuits as random-access memory (RAM) cells that have to be addressed and coupled to sense amplifiers to read the data they contain.
Because small geometry transistor devices such as FinFET transistors cannot individually support the voltages necessary for programming and erasing ReRAM devices, two FinFET transistors have been placed in series in addressable ReRAM memory cells.
Referring first of all to FIGS. 1, 2A and 2B, a schematic diagram of a portion 10 of a prior-art ReRAM memory array, a top view of a layout of a portion of the memory array 10 shown in FIG. 1, and a cross-sectional view of the layout of the portion of the memory array shown in FIG. 2A taken through lines 2B-2B are shown, respectively. In FIG. 1, a portion 10 of a prior-art ReRAM memory array includes six ReRAM memory cells (indicated in dashed lines at reference numerals 12a through 12f, respectively). ReRAM memory cells 12a, 12b, and 12c are in a first column of the array and ReRAM memory cells 12d, 12e, and 12f are in a second column of the array. Persons of ordinary skill in the art will observe that the layout of the memory cells 12a through 12f is a mirror configuration. Thus, in the first column of the array memory cells 12a and 12b mirror each other do memory cells 12b and 12c Similar mirroring exists in the second column of the array.
Each memory cell 12a through 12f includes a ReRAM device and two series-connected transistor devices. These circuit elements will be designated using the letter suffixes corresponding to the memory cells in which they are disposed. As an example, ReRAM memory cell 12a includes ReRAM device 14a, and two n-channel FinFET transistor devices 16a and 18a all connected in series between a first common bias node 20-1 and a first bit line BL0 at reference numeral 22-1 associated with a first column of the portion 10 of the array. The convention used in the drawing symbol of the ReRAM devices herein is that the wider end of the ReRAM device is the ion source side of the device and the narrower end is the opposing electrode, which is separated from the ion source by a solid electrolyte layer. To program a ReRAM device, i.e., to set it to a lower resistance, a programming voltage is applied with the most positive potential applied to the wider end of the ReRAM device. To erase a ReRAM device, i.e., to set it to a high resistance, a programming voltage is applied with the most positive potential applied to the narrower end of the ReRAM device.
ReRAM memory cell 12b includes ReRAM device 14b, and two n-channel FinFET transistor devices 16b and 18b all connected in series between a second common bias node 20-2 and the first bit line 22-1. ReRAM memory cell 12c includes ReRAM device 14c, and two n-channel FinFET transistor devices 16c and 18c all connected in series between the second common bias node 20-2 and the first bit line 22-1. The ReRAM cells 12d, 12e, and 12f are similarly connected except that they are connected between the common bias nodes 20-1 and 20-2, respectively, and a second bit line 22-2 associated with a second column of the portion 10 of the array.
The gates of the two FinFET transistors in each row of the array are connected in common to a word line. Thus, the FinFET transistors 16a and 18a and 16d and 18d are connected together to a word line WL0 at reference numeral 24. The word line 24 is shown in two sections, each of which represents a gate line formed from, for example, a metal or metal silicide, that runs the length of the row in the array containing the ReRAM memory cells 12a and 12d. These gate lines are stitched together as represented by connection 26. Similarly, the gates of the FinFET transistors 16b and 18b and 16e and 18e are connected together to the word lines WL1 at reference numeral 28. These gate lines are stitched together as represented by connection 30. The gates of the FinFET transistors 16c and 18c and 16f and 18f are connected together to the word lines WL2 at reference numeral 32. These gate lines are stitched together as represented by connection 34.
Referring now to both FIGS. 2A and 2B, diagrams show a typical layout 40 for an implementation in an integrated circuit of ReRAM memory cells like those of FIG. 1A. The portion of the ReRAM array depicted in FIGS. 2A and 2B is shown within dashed lines 36 of FIG. 1. Accordingly, persons of ordinary skill in the art will note that the layout depicted in FIGS. 2A and 2B do not include the ReRAM cells 12c and 12f depicted in FIG. 1. Where elements of FIG. 1 are depicted in FIGS. 2A and 2B, they will be designated using the same reference numerals used for these elements in FIG. 1.
A first group of fins 42, represented as a diffusion in FIG. 2A for simplicity, forms the source, drains, and channels for the FinFET transistors 16a, 18a, 16b, and 18b of the first column of the array and a second the group of fins 44 forms the source, drains, and channels for the FinFET transistors 16d, 18d, 16e, and 18e in the second column of the array. Dashed lines indicated at reference numerals 12a, 12b, 12d, and 12e in FIG. 2A show the locations of ReRAM memory cells 12a, 12b, 12d, and 12e of FIG. 1.
Gate electrode line 46 forms the gates for FinFET transistors 16a and 16d, and serves as word line WL0. Gate line 48 forms the gates for FinFET transistors 18a and 18d and also serves as word line WL0 (as shown in FIG. 1 and FIG. 2A by connection 26). Gate electrode line 50 forms the gates for FinFET transistors 16b and 16e and serves as word line WL1. Gate electrode line 52 forms the gates for FinFET transistors 18b and 18e and also serves as word line WL1 (as shown in FIG. 1 and FIG. 2A by connection 30). Gate electrode lines 46, 48, 50, and 52 are formed from metal as is known in the FinFET fabrication art.
FinFET technology requires a dummy gate electrode to terminate the ends of a diffusion region to isolate it from adjoining diffusion regions. The dummy gate electrodes are formed at the same time as and in the same manner as the gate electrode lines 46, 48, 50, and 52, and are referred to as dummy gate electrodes because no transistors are formed under them. Dummy gate electrode line 54 provides isolation between ReRAM devices 14a, 14d and ReRAM devices (not shown) that are disposed above dummy gate electrode line 54. Similarly, dummy gate electrode line 56 provides isolation between ReRAM devices 14b, 14e and ReRAM devices (not shown) that are disposed below gate electrode line 56.
Reference numerals 58 in FIG. 2B indicate the gate dielectric layers below the gate electrode lines 46, 48, 50, 54, and 56. Contacts 60 and 62 connect the gate electrode lines 46 and 48 to a metal level 0 (M0) segment 64 (identified as stitch connection 26 in FIG. 1) that connects the gates of FinFETs 16a and 18a together. Contacts 66 and 68 connect the gate lines 50 and 52 to a M0 segment 70 (identified as stitch connection 30 in FIG. 1) that connects the gates of FinFETs 16b and 18b together.
Metal level 0 (M0) segment 72-1 is connected to the group of fins 42 by contact 74 shown in FIG. 2B. Contact 76 connects M0 segment 72-1 to a metal level 1 (M1) segment 78. Contact 80 connects M1 segment 78 to a metal level 2 (M2) segment 82. Contact 84, shown in both FIGS. 2A and 2B connects M2 segment 82 to a metal level 3 (M3) segment 86 that serves as the bit line 22-1 in FIG. 1. Metal segments 78 and 82 and contacts 76 and 80 are not shown in FIG. 2A to avoid overcomplicating the drawing.
Metal layer 2 segment 88 serves as the first common bias node 20-1 in FIG. 1. A contact 90-1 connects the M2 segment 88 to the ReRAM 14a of FIG. 1, shown in FIG. 2A and also shown in FIG. 2B as including an ion source layer 92 and solid electrolyte layer 94. Persons skilled in the art will appreciate that the ReRAM devices are known and are more complicated that as shown in FIG. 2B. As shown in FIG. 2B, the ReRAM device 14a is connected to FinFET transistor 16a through contact 96 to M1 layer segment 98, contact 100 to M0 segment 102-1, and contact 104.
Metal layer 2 segment 106 serves as the second common bias node 20-2 in FIG. 1. a contact 90-2 connects the M2 segment 106 to the ReRAM 14b of FIG. 1, shown in FIG. 2A and also shown in FIG. 2B as including an ion source layer 108 and solid electrolyte layer 110. Persons skilled in the art will appreciate that the ReRAM devices are known and are more complicated that as shown in FIG. 2B. As shown in FIG. 2B, the ReRAM device 14b is connected to FinFET transistor 16b through contact 112 to M1 layer segment 114, contact 116 to M0 segment 102-2, and contact 118.
To program ReRAM device 14a in memory cell 12a in FIG. 1, a positive voltage is applied to word line WL0 24 to turn on transistors 16a and 18a and a voltage is applied between bias line 20-1 and bit line 0 22-1 with the more positive potential applied to bias line 20-1. To erase ReRAM device 14a in memory cell 12a in FIG. 1, a positive voltage is applied to word line WL0 24 to turn on transistors 16a and 18a and a voltage is applied between bias line 20-1 and bit line 0 22-1 with the more positive potential applied to bit line 0 22-1. To inhibit programming/erasing of ReRAM devices 14b and 14c in memory cells 12b and 12c, word lines WL1 28 and WL2 32 are turned off. To inhibit programming/erasing of ReRAM devices 14d, 14e, and 14f in memory cells 12d, 12e, and 12f the voltage at bit line 1 22-2 is set to the same voltage as bias line 0 20-1.
Under the biasing conditions that are present for programming a ReRAM memory cell (using memory cell 12a as an example), the transistors 16a and 18a are in common source configuration which provides current limiting. In addition, since both transistors 16a and 18a are turned on, the voltage across them is close to zero resulting in little or no stress on these transistors. In the reverse direction for erasing a ReRAM device (using memory cell 12a as an example), there is no current limiting because neither of the FinFET transistors of the selected ReRAM cell is connected to ground (i.e., in common source configuration) and the changing resistance of the ReRAM device 14a places a source bias on the transistors 16a and 18a, reducing their current handling capabilities. In addition, a higher voltage is present across the transistors 16a and 18a than during programming, requiring a larger number of FinFET transistors to support the voltage. This requirement places a limit on the area minimization of ReRAM memory cells.
In addition, ReRAM memory cells require programming and erase currents of about 100 μA or more. In order to provide such current, the programming and erase paths must have an impedance low enough to allow programming and erase currents of this magnitude to flow. As device sizes decrease, the transistors used become smaller and weaker and wider metal lines are needed to supply the necessary programming potentials. In addition, as noted above with respect to FIG. 2A, prior-art ReRAM memory arrays employing ReRAM memory cells fabricated using deep submicron lines (i.e., FinFET transistor devices) require quantized layout rules that employ the additional dummy gate lines (e.g., dummy gate lines 54 and 56 in FIG. 2A) to terminate diffusion regions between cells.